Sun UltraSPARC
Research conducted at Berkeley between 1980 and 1984 on RISC architectures, carried out in parallel with Stanford’s work on MIPS, led to the creation of Scalable Processor ARChitecture (SPARC) by Sun Microsystems in 1985. Four years later, Sun founded SPARC International to open this architecture to other manufacturers.
The first version, SPARC V7, was released in 1986. V8 arrived in 1990 with hardware support for multiplication and division, an MMU, and 128-bit floating-point operations. V9 represented a major milestone: it handled 64-bit registers and operations, redesigned exception handling, and integrated prefetching.
In 1995, Sun launched the first UltraSPARC, the first processor to integrate SPARC V9. Marc Tremblay participated in its design. This superscalar microprocessor executed instructions out of order and processed four simultaneously. Its pipeline had eight stages. Engineers had simplified the execution unit compared to the SuperSPARC to gain frequency, particularly by modifying the ALU branching.
The processor featured 32 64-bit registers divided into eight windows, totaling 144 registers. This technique prevented called functions from wasting time saving and then restoring registers. Seven input registers and three output registers provided access to two ALUs and the memory management unit. A single ALU handled multiplication and division.
The floating-point unit was divided into five blocks: addition and subtraction, multiplication, division and square roots, followed by two blocks dedicated to SIMD instructions of the Visual Instruction Set. Thirty-two 64-bit registers served these operations, including five for inputs and three for outputs.
The primary cache was divided into two 16 KB sections, one for instructions and one for data. An external unified secondary cache was to complement the system, with a capacity between 512 KB and 4 MB, accessible in one cycle. This cache used synchronous SRAM clocked at the processor speed.
Texas Instruments manufactured UltraSPARC using the EPIC-3 CMOS process at 0.5 μm on four metal layers. The manufacturer abandoned BiCMOS, which offered little advantage at this level of miniaturization. The chip integrated 3.8 million transistors in a 521-pin PBGA package.
Ten years later, the UltraSPARC T1 broke with this approach. Sun embodied its concept of throughput computing, which favored multiplying cores and threads over increasing frequencies or making pipelines more complex. In its full version, the T1 had eight cores each executing four threads, for a total of 32 threads. Sun sacrificed floating-point performance and cache size in favor of parallelism.
The T1 used a short in-order execution pipeline: fetch, thread selection, decode, execute, memory, and write-back. Its ALUs operated with a latency of one cycle, multipliers and dividers over multiple cycles. A single floating-point unit was shared among the eight cores. Each thread had its own instruction buffer.
The processor switched between threads according to several rules. By default, it alternated between available threads using an LRU policy. Long instructions triggered a thread switch to keep the pipeline active. The L1 cache was flow-through, with the L2 including the L1. The T1 deliberately made do with a reduced cache: the large number of threads masked memory latencies.
The UltraSPARC T1 embedded a hypervisor that added a privilege level above user and supervisor modes. This lightweight software layer offered a complete virtualization interface to guest systems. Sun fully documented this API and released the T1 VHDL sources under an open license, renamed OpenSPARC T1.
The T1 consumed no more than 70 watts, half that of a Xeon or an Itanium. This efficiency mattered for data centers where air conditioning could cost more than the hardware itself.
This architecture suited web servers, client-server applications, and certain databases that exploited its high parallelism. Sun acknowledged that scientific workloads, especially those making heavy use of floating-point operations, were not these processors’ forte.
UltraSPARC reflects the evolution of processor architectures, from early RISC to massively multicore designs. It demonstrates the strategies explored to increase performance: pipeline complexity on one hand, massive parallelization on the other.